The present invention relates to calibrating first and second signals to each other, and in particular, to a system for compensating a ramp signal by calibrating the ramp signal to the level of a compensating signal. In particular, the compensating signal may be the output of an error amplifier which produces a signal proportional to a difference between a voltage feedback signal of a power factor correction stage of a DC to DC converter and a reference signal. The ramp signal is utilized to control the pulse width modulation of the controlled output switch, for example, the power factor correction (PFC) output stage or the switch or switches of the DC to DC converter. In a typical application, the ramp signal is provided to one input of a PWM comparator and the other input of the comparator is provided with the output of the error amplifier whereby the output of the PWM comparator comprises a pulse width modulated signal whose duty cycle controls the switching of the output stage.
It is desirable to calibrate the ramp signal to the compensating signal, for example, the output of the error amplifier, in order to achieve high accuracy PFC.
A critical requirement in achieving near ideal Power Factor Correction (PFC) in a Single Cycle PFC Controller is to establish a Pulse Width Modulation (PWM) ramp waveform that represents the mathematical integration of an error voltage (COMP) on a cycle-by-cycle basis. The integration is reset to zero at the beginning of each switching clock cycle with the integration continuing throughout the entire cycle. The duration of one switching cycle is determined by the controller switching frequency. For a fixed COMP error voltage, the PWM ramp waveform will start at zero volts at the beginning of each switching cycle, linearly rise over the period, and then terminate at the COMP voltage at the completion of each cycle.
During operation, the COMP voltage is continually moving with input line frequency in an effort to provide the highest PFC quality. Since changes in the COMP voltage occur at a much slower frequency compared to the controller switching frequency, it is valid to assume the COMP voltage is “fixed”. FIG. 1 below graphically details the desired RAMP waveform for two different COMP voltages, VCOMP 1 and VCOMP2. In each case, at the end of the cycle, it is desired that the ramp terminate at the level of the compensating voltage.
The difficulty arises when non-ideal circuit parameters such as op-amp offsets, circuit response times, package stress variations, temperature and process variations begin to introduce errors in the RAMP slope. Furthermore, a large contributor to ramp error in single cycle controllers (for example the IR1150) is that the user can program the switching frequency from 50 KHz to 200 KHz which means the RAMP slope needs to track a 4× change in frequency. This is difficult to implement under tight accuracy requirements due to mismatches between the oscillator and ramp capacitors, charge currents, circuit delays, and threshold voltages.